The present invention relates to an interrupt control system between processing modules in a data processing system having a main memory and a plurality of processing modules which are connected to a common bus.
In a conventional data processing system having a main memory and a plurality of processing modules which are connected to a common bus, interrupt control between the processing modules is performed between a central processing unit (CPU) and an I/O device.
An interrupt occurs in the following cases:
(1) at a time when the I/O device notifies the CPU of an end to I/O operation thereof, performed by an instruction from the CPU,
(2) at a time when the I/O device notifies the CPU of a transient state such as power-off of the activated I/O device, and
(3) at a time when the I/O device, through which connection between the CPU and another system is made, notifies the CPU that a communication to the CPU is required by the system.
The CPU detects an I/O device interrupt request signal and returns an interrupt acknowledge signal to the corresponding I/O device. When the I/O device receives the interrupt acknowledge signal, it resets the interrupt request signal.
In order to identify which of the cases (1), (2), and (3) causes a current interrupt in a conventional scheme, for example, an interrupt cause must be written in the main memory before the I/O device generates an interrupt request. The CPU accesses the main memory when the I/O device generates the interrupt request, thereby detecting the interrupt cause.
Alternatively, the interrupt cause can be transmitted from the I/O to the CPU through a data bus when the CPU returns the interrupt acknowledge signal to the I/O.
When an interrupt sequence is performed between the CPU and a plurality of I/O devices, various methods can be considered in order to permit the CPU to detect an I/O device which generates the interrupt request signal. Typical examples will be described with reference to FIGS. 1 and 2. In the conventional system of FIG. 1, interrupt request signal lines L-IRA and L-IRB are connected between the CPU and I/O devices A and B, respectively, and through these lines the CPU can detect which device generated the interrupt request signal. In another conventional system, that of FIG. 2, interrupt request signal lines L2 of I/O devices A and B are wired-OR. The CPU returns the interrupt acknowledge signal to the I/O in response to an interrupt request signal from one or a plurality of I/O devices. Among these I/O devices which request an interrupt, the I/O device having the highest priority responds to the interrupt acknowledge signal and transmits, through line L1, I/O device identification data such as an I/O device address, so that the CPU can identify the proper I/O device. In the system configuration of FIG. 2, for example, when an I/O device A generates the interrupt request signal, the device A sends its assigned device self-address to the CPU while the interrupt acknowledge signal is not being transmitted as an interrupt acknowledge signal B to the I/O device B. However, when the I/O device A does not generate the interrupt request signal, the I/O device A transmits the interrupt acknowledge signal A to the I/O device B as the interrupt acknowledge signal B through the corresponding I/O device address line. When the I/O device B generates the interrupt request signal, it sends its, assigned device self-address to the CPU. This connection technique is called a daisy chain.
The conventional interrupt control systems described above have the following drawbacks.
In the system of FIG. 1, independent interrupt request lines must be arranged for asynchronous interrupt requests from a plurality of I/O devices. A large volume of hardware is required to control a large number of I/O devices, and interconnections between the devices are complex.
Although the system of FIG. 2 is suitable for a large scale system, I/O interrupt transmission hardware, I/O address response hardware and CPU I/O address input hardware are required. Furthermore, the interrupt priority is sequentially determined (i.e., the I/O nearest the CPU has the highest priority), and thus system flexibility is poor, resulting in inconvenience.